1. Technical Field of the Invention
The invention relates to a method of fabricating a semiconductor device. More particularly, the invention is directed to a method of fabricating a nonvolatile memory device in which a high-k dielectric layer is used as an upper insulating layer of a cell gate insulating layer.
2. Description of the Related Art
Generally, a semiconductor memory device includes a plurality of cell transistors and function circuits for operating the cell transistors. The semiconductor memory device may be categorized as either volatile memory devices or nonvolatile memory devices depending on whether stored information can be retained when their power supplies are interrupted. The volatile memory device is classified into a dynamic random access memory (DRAM) and a static random access memory (SRAM). The nonvolatile memory device is classified into a read only memory (ROM), an erasable and programmable ROM (EPROM), and an electrically erasable and programmable ROM (EEPROM). Recently, demand for the EEPROM has been increasing with the trend toward portability and miniaturization of electronic appliances.
A typical type of EEPROM is a floating gate type flash memory device having an electrically isolated conductive pattern (i.e., a floating gate). In order to change information stored in the cell transistor, Fowler-Nordheim (F-N) tunneling is used in the floating gate type flash memory device. F-N tunneling is a quantum-mechanical phenomenon caused by a high potential difference. Low voltage transistors and high voltage transistors are used for the function circuit of the floating gate type flash memory device. Generally, the high voltage transistor has a junction region of a DDD structure, and the low voltage transistor has a junction region of a LDD structure. Also, the high voltage transistor has a thick gate insulating layer as compared to the low voltage transistor. Accordingly, the floating gate type flash memory device includes three different gate insulating layers for the cell transistor, the high voltage transistor and the low voltage transistor.
Generally, in order to simplify processes, oxide layers are used as the gate insulating layer in the low voltage transistor and the cell transistor. Here, the oxide layers are simultaneously formed to have a uniform thickness. Thus, the floating gate type flash memory device includes two gate insulating layers, i.e., a low voltage gate insulating layer used in the cell transistor and the low voltage transistor and a high voltage gate insulating layer used in the high voltage transistor.
Meanwhile, another type of the EEPROM is a trap type flash memory device in which an insulating layer is used as a charge storage structure instead of the floating gate. The trap type flash memory device includes a cell gate insulating layer composed of a lower silicon oxide layer, a silicon nitride layer, and an upper silicon oxide layer, which are sequentially stacked. Here, the silicon nitride layer is used as a charge storage layer of the trap type flash memory device. Unlike the floating gate type flash memory device, a low voltage gate insulating layer cannot be used as the cell gate insulating layer in the trap type flash memory device. Accordingly, the trap type flash memory device should include the gate insulating layers having three different thicknesses.
In the trap type flash memory device, a method of forming the gate insulating layer having three different thicknesses includes forming the high voltage gate insulating layer at the high voltage transistor region. Thereafter, the cell gate insulating layer is formed on an entire surface of a semiconductor substrate. The cell gate insulating layer is patterned to form a cell gate insulating pattern covering the cell transistor region and exposing the low voltage transistor region and the high voltage transistor region. Next, the low voltage gate insulating layer is formed at the exposed semiconductor substrate in the low voltage transistor region.
During a process of patterning the cell gate insulating layer, photolithography and etching processes are performed using a photoresist layer. In this case, the upper silicon oxide layer is thin. Thus, the upper silicon oxide layer is damaged or its thickness thereof is reduced during the photolithographic process and a subsequent process of removing the photoresist layer. Therefore, characteristics of the trap type flash memory device may be degraded.